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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/11160

Title: A 4PAM/2PAM Coaxial Cable Receiver Analog Front-end Targeting 40Gb/s in 90-nm CMOS
Authors: Park, Peter
Advisor: Chan Carusone, Anthony
Department: Electrical and Computer Engineering
Keywords: electrical engineering
electronics
equalization
CMOS
4-PAM
PAM4
Issue Date: 30-Jul-2008
Abstract: A 4-PAM/2-PAM receiver analog front-end (AFE) targeting 20GSymbol/s for use with coaxial cable channels is presented. Behavioral simulations incorporate a transmitter, scalable coaxial cable model, and the proposed receiver architecture, targeting cable loss of 32dB at 10GHz. To accommodate links of varying lengths, the AFE includes a variable-gain amplifier (VGA) and analog peaking equalizer. The input preamplifier is important for achieving the required input sensitivity. A DC bias current is introduced through the feedback resistor in a conventional shunt-shunt feedback nMOS transimpedance amplifier (TIA) to level-shift the output, obviating a following level-shifting stage. The fabricated AFE occupies 0.89mm2 in a 90-nm CMOS process and dissipates 138mW from a 1.3V supply. The AFE amplifies and opens the eye pattern of a 20-Gb/s 2-PAM data stream transmitted over coaxial cable with 7.5dB loss at 10GHz.
URI: http://hdl.handle.net/1807/11160
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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