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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/18248

Title: Circuit Debugging with Error Trace Compaction and Maximum Satisfiability
Authors: Chen, Yibin
Advisor: Veneris, Andreas
Department: Electrical and Computer Engineering
Keywords: Circuit Debugging
Formal Methods
Issue Date: 13-Jan-2010
Abstract: Improving the performance and functionality of contemporary debugging tools is essential to alleviate the debugging task. This dissertation aims at narrowing the gap between current capabilities of debugging tools and industry requirements by improving two important debugging techniques: error trace compaction and automated debugging. Error trace compaction leverages incremental SAT and heuristics to reduce the number of clock cycles required to observe a failure in an error trace. The technique presented reduces the length of the error trace to a minimum while improving performance by 8× compared to a previous technique. The second contribution uses maximum satisfiability to enhance the functionality and performance of automated debuggers. The method proposed can identify where in the design the bug is located and when in the error trace the bug is excited. Compared to a competitive SAT-based approach, our formulation produces problems that are 80% smaller and that can be solved 4.5x faster.
URI: http://hdl.handle.net/1807/18248
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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