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|Title: ||A High-performance, Reconfigurable Architecture for Restricted Boltzmann Machines|
|Authors: ||Ly, Daniel Le|
|Advisor: ||Chow, Paul|
|Department: ||Electrical and Computer Engineering|
|Keywords: ||Reconfigurable Architecture|
High Performance Computing
|Issue Date: ||15-Feb-2010|
|Abstract: ||Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of adoption is due to the fact that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can take advantage of the inherent parallelism in neural networks is desired.
This thesis investigates how the Restricted Boltzmann machine, a popular type of neural network, can be effectively mapped to a high-performance hardware architecture on FPGA platforms. The proposed, modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100MHz through a variety of different configurations. The maximum performance was obtained by instantiating a Restricted Boltzmann Machine of 256x256 nodes distributed across four FPGAs, which results in a computational speed of 3.13 billion connection-updates-per-second and a speed-up of 145-fold over an optimized C program running on a 2.8GHz Intel processor.|
|Appears in Collections:||Master|
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses
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