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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/19001

Title: Coherent Shared Memories for FPGAs
Authors: Woods, David
Advisor: Chow, Paul
Department: Electrical and Computer Engineering
Keywords: FPGA
Computer Engineering
Caching
Shared Memory
Issue Date: 17-Feb-2010
Abstract: To build a shared-memory programming model for FPGAs, a fast and highly parallel method of accessing the shared-memory is required. This thesis presents a first look at how to implement a coherent caching system in an FPGA. The coherent caching system consists of multiple distributed caches that implement the write-once coherence protocol, allowing efficient access to system memory while simplifying the user programming model. Several test applications are used to verify functionality, and assess performance of the current system. Results show that with a processor-based system, some applications could benefit from improvements to the coherence system, but for many applications, the current system is sufficient. However, the current coherent caching system is not sufficient for most hardware core based systems, because the faster memory accesses quickly saturate shared system resources. As well, the performance of distributed-memory systems currently surpasses that of the coherent caching system. Performance results are promising, and given the potential for improvements, future work on this system is warranted.
URI: http://hdl.handle.net/1807/19001
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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