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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/24280

Title: Roko: Balancing Performance and Usability in Coarse-grain Parallelization
Authors: Segulja, Cedomir
Advisor: Abdelrahman, Tarek S.
Department: Electrical and Computer Engineering
Keywords: Programming Model
Parallelization
Synchronization
Concurrency Control
Multi-core Systems
FPGA Applications
Issue Date: 6-Apr-2010
Abstract: We present Roko, a system that allows parallelization of sequential C codes with a modest user intervention. The user exposes parallelism at the function level by annotating the code with pragmas. Roko defines only two pragmas: the parallel pragma is used to denote function calls that will be executed asynchronously, and the exposed pragma is used to describe data usage of the marked function calls. Architecturally, Roko consists of three components: a compiler that analyzes pragmas, a software environment that spreads the execution over multiple processors, and a hardware support that implements a novel synchronization scheme, versioning. We have designed, implemented and evaluated an FPGA-based prototype of Roko. Our experimental evaluation shows: (i) that few simple pragmas are all that is needed to expose parallelism in benchmark applications and (ii) that Roko can deliver good performance in terms of application speedup.
URI: http://hdl.handle.net/1807/24280
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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