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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/24329

Title: Power MOSFETs with Enhanced Electrical Characteristics
Authors: Wang, Hao
Advisor: Ng, Wai Tung
Department: Materials Science and Engineering
Keywords: Power MOSFETs
Issue Date: 13-Apr-2010
Abstract: The integration of high voltage power transistors with control circuitry to form smart Power Integrated Circuits (PIC) has numerous applications in the areas of industrial and consumer electronics. These smart PICs must rely on the availability of high performance power transistors. In this thesis, a vertical U-shaped gate MOSFET (UMOS) and a lateral Extended Drain MOSFET (EDMOS) with enhanced electrical characteristics are proposed, developed and verified via experimental fabrication. The proposed new process and structure offers superior performance, such as low on-resistance, low gate charge and optimized high breakdown voltage. In the vertical power UMOS, a novel trenched Local Oxidation of Silicon (LOCOS) process has been applied to the vertical gate structure to reduce the gate-to-source overlap capacitance (Cgs). A 40% reduction in Cgs is achieved when compared to conventional UMOS. A specific on-resistance Ron, sp = 60m2·mm2 is observed, which is 45% better than that of the conventional UMOS. The improvement in the device’s Figure-of-Merit (FOM = Ron × Qg) is about 58%. A floating RESURF EDMOS (BV=55V, Ron,sp=36.5m2·mm2) with a 400% improvement in the Safe Operating Area (SOA) when compared to the conventional EDMOS structure is also presented. The proposed EDMOS employs both drain and iii source engineering to enhance SOA, not only via reducing the base resistance of the parasitic bipolar transistor, but also suppressing the base current of the parasitic bipolar transistor under high Vgs and high Vds conditions. A buried deep Nwell allows the device to have better trade-off between breakdown voltage and on-resistance. Finally, in order to achieve low gate charge in the EDMOS, a novel orthogonal gate electrode is proposed to reduce the gate-to-drain overlap capacitance (Cgd). The orthogonal gate has both horizontal and vertical sections for gate control. This device is implemented in a 0.18?m 30V HV-CMOS process. Compared to a conventional EDMOS with the same voltage and size, a 75% Cgd reduction is observed. The FOM is improved by 53%.
URI: http://hdl.handle.net/1807/24329
Appears in Collections:Doctoral
Department of Materials Science & Engineering - Doctoral theses

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