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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/24601

Title: A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs
Authors: Luu, Jason
Advisor: Rose, Jonathan S.
Anderson, Jason
Department: Electrical and Computer Engineering
Keywords: FPGA
Field-Programmable Gate Arrays
Computer-Aided Design
Issue Date: 27-Jul-2010
Abstract: The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.
URI: http://hdl.handle.net/1807/24601
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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