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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/24895

Title: Enhanced Synchronous Design Using Asynchronous Techniques
Authors: Toosizadeh, Navid
Advisor: Zaky, Safwat
Department: Electrical and Computer Engineering
Keywords: Digital Design
PVT-aware
Issue Date: 1-Sep-2010
Abstract: As semiconductor technology scales down, process variations become increasingly difficult to control. To cope with this, more and more conservative delay and clock frequency estimations are used during design, which result in overly large and leaky circuits. Also, the system runs at a speed slower than that possible because a fixed clock determined by the worst-case analysis of the circuit is used. On top of process variations, voltage and temperature variations also push the designer towards even more conservative delay estimations. On the other hand, asynchronous design style has potential advantages over synchronous design including resilience to process variations, lower power consumption and higher performance. Unfortunately, these advantages are usually hindered by the significant design effort required to implement useful asynchronous circuits and also by the overhead of asynchronous control logic. Borrowing from asynchronous techniques, a new methodology is proposed to design synchronous circuits that have some of the advantages of asynchronous circuits. Asynchronous logic is used to generate the clock of a synchronous system. The resulting system automatically tunes itself to deliver the best-possible performance under the prevailing process-voltage-temperature (PVT) conditions. This methodology may be used to reduce the leakage power significantly in deep nanometer technologies. It also helps in handling process variations. The results from a 32-bit processor implemented in 90nm technology shows 10X leakage reduction compared to the traditional synchronous design. The proposed technique is expanded to adjust the speed of a pipeline according to the current operations flowing in the pipeline as well as the current PVT conditions. The results from a 32-bit processor in 90nm technology demonstrate a 2X speed improvement compared to the conventional synchronous design. The proposed techniques only use synchronous design tools and are compatible with design flows that are currently in use.
URI: http://hdl.handle.net/1807/24895
Appears in Collections:Doctoral
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Doctoral theses

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