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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/25473

Title: Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor
Authors: Dewan-Sandur, B. P.
Kaisare, A.
Agonafer, De.
Agonafer, Da.
Amon, C.
Pekin, S.
Dishongh, T.
Keywords: electronic design automation
integrated circuit packaging
integrated logic circuits
integrated memory circuits
mesh generation
microprocessor chips
thermal conductivity
thermal management (packaging)
100 C
PCB thermal conductivity
Pro/Engineer CAD tool
Wildfire 2.0 CAD tool
computer-aided-design tool
copper heat spreader
die stacking architecture
heat transfer coefficient
integrated circuit packagin
logic processor
memory processor
meshed analysis
package-on-package technology
thermal design specification
Issue Date: 5-Jul-2006
Publisher: IEEE
Citation: Dewan-Sandur BP, Kaisare A, Agonafer D, Agonafer D, Amon C, Pekin S, et al. In: Thermal management of die stacking architecture that includes memory and logic processor. Electronic components and technology conference proceedings 56th; May 30 - June 2; San Diego, CA, USA. IEEE; 2006. p. 1963-8.
Series/Report no.: Electronic Components and Technology Conference, 2006. Proceedings. 56th
Abstract: The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineerreg Wildfiretrade 2.0 as a computer-aided-design (CAD) tool and were transferred to ANSYSreg Workbenchtrade10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100degC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements
Description: Originally published in Electronic Components and Technology Conference, 2006. Proceedings. 56th by IEEE. IEEE holds all copyright of this article. IEEE allows the final published version of author's own work to be deposited in institutional repositories.
URI: http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=1645929&queryText%3DThermal+Management+of+Die+Stacking+Architecture+That+Includes+Memory+and+Logic+Processor%26openedRefinements%3D*%26searchField%3DSearch+All
ISBN: 1-4244-0152-6
ISSN: 0569-5503
Appears in Collections:Faculty of Applied Science and Engineering Office of the Dean

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