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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/25529

Title: VLSI Implementation of Lattice Reduction for MIMO Wireless Communication Systems
Authors: Youssef, Ameer
Advisor: Gulak, P. Glenn
Department: Electrical and Computer Engineering
Keywords: MIMO Systems
Lattice Reduction
VLSI Implementation
Wireless Communication
Issue Date: 31-Dec-2010
Abstract: Lattice-Reduction has become a popular way of improving the performance of MIMO detectors. However, developing an efficient high-throughput VLSI implementation of LR has been a major challenge in the literature. This thesis proposes a hardware-optimized version of the popular LLL algorithm that reduces its complexity by 70% and achieves a fixed runtime while maintaining ML diversity. The proposed algorithm is implemented for 4x4 MIMO systems and uses a novel pipelined architecture that achieves a fixed low processing latency of 40 cycles, resulting in a fixed throughput that is independent of the channel correlation. The proposed LR core, fabricated in 0.13um CMOS, is the first fabricated and tested LR ASIC implementation in the literature. Test results show that the LR core achieves a maximum clock rate of 204 MHz, yielding a throughput of 510 Mbps, thus satisfying the aggressive throughput requirements of emerging 4G wireless standards, such as IEEE-802.16m and LTE-Advanced.
URI: http://hdl.handle.net/1807/25529
Appears in Collections:Master
The Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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