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 Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/25602

 Title: On-chip Power Grid Verification with Reduced Order Modeling Authors: Goyal, Ankit Advisor: Najm, Farid N. Department: Electrical and Computer Engineering Keywords: Power Grid Integrity AnalysisModel Order Reduction Issue Date: 31-Dec-2010 Abstract: To ensure the robustness of an integrated circuit design, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order Reduction (MOR) techniques to reduce the size of power grids but their focus is more on simulation. In verification, we are concerned about the safety of nodes, including the ones which have been eliminated in the reduction process. This work proposes a novel approach to systematically reduce the power grid and accurately compute an upper bound on the voltage drops at power grid nodes which are retained. Furthermore, a criterion for the safety of nodes which are removed is established based on the safety of other nearby nodes and a user specified margin. URI: http://hdl.handle.net/1807/25602 Appears in Collections: MasterThe Edward S. Rogers Sr. Department of Electrical & Computer Engineering - Master theses

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