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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/25856

Title: An Interconnection Network for a Cache Coherent System on FPGAs
Authors: Mirian, Vincent
Advisor: Chow, Paul
Department: Electrical and Computer Engineering
Keywords: FPGA
Cache Coherence
Interconnection Network
Pthread (Posix Thread)
programming model
parrallel programming
shared-memory model
Issue Date: 12-Jan-2011
Abstract: Field-Programmable Gate Arrays (FPGAs) systems now comprise many processing elements that are processors running software and hardware engines used to accelerate specific functions. To make the programming of such a system simpler, it is easiest to think of a shared-memory environment, much like in current multi-core processor systems. This thesis introduces a novel, shared-memory, cache-coherent infrastructure for heterogeneous systems implemented on FPGAs that can then form the basis of a shared-memory programming model for heterogeneous systems. With simulation results, it is shown that the cache-coherent infrastructure outperforms the infrastructure of Woods [1] with a speedup of 1.10. The thesis explores the various configurations of the cache interconnection network and the benefit of the cache-to-cache cache line data transfer with its impact on main memory access. Finally, the thesis shows the cache-coherent infrastructure has very little overhead when using its cache coherence implementation.
URI: http://hdl.handle.net/1807/25856
Appears in Collections:Master

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