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|Title: ||Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage Power MOSFETs|
|Authors: ||Yoo, Abraham|
|Advisor: ||Ng, Wai Tung|
|Department: ||Materials Science and Engineering|
|Keywords: ||power MOSFETs|
|Issue Date: ||23-Feb-2011|
|Abstract: ||In this thesis, next generation low-voltage integrated power semiconductor devices are proposed and analyzed in terms of device structure and layout optimization techniques. Both approaches strive to minimize the power consumption of the output stage in DC-DC converters.
In the first part of this thesis, we present a low-voltage CMOS power transistor layout technique, implemented in a 0.25µm, 5 metal layer standard CMOS process. The hybrid waffle (HW) layout was designed to provide an effective trade-off between the width of diagonal source/drain metal and the active device area, allowing more effective optimization between switching and conduction losses. In comparison with conventional layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with 3.6 times smaller total gate charge for CMOS devices with a current rating of 1A. Integrated DC-DC buck converters using HW output stages were found to have higher efficiencies at switching frequencies beyond multi-MHz.
In the second part of the thesis, we present a CMOS-compatible lateral superjunction FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ devices is that the on-resistance is not only strongly dependent on the drift doping concentration but also on the channel resistance as well. To resolve the issue, a SJ-FINFET structure consisting of a 3D trench gate and SJ drift region was developed to minimize both channel and drift resistances. Several prototype devices were fabricated in a 0.5µm CMOS compatible process with nine masking layers. In comparison with conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately 30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become a competitive power device for sub-100V rating applications.|
|Appears in Collections:||Doctoral|
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