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T-Space at The University of Toronto Libraries >
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Master >

Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/29987

Title: A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS
Authors: Sarvari, Siamak
Advisor: Sheikholeslami, Ali
Department: Electrical and Computer Engineering
Keywords: high-speed signaling
decision-feedback equalizer (DFE)
blind sampling
ADC-based receiver
speculative
look-ahead
clock and data recovery (CDR)
blind oversampling
CMOS
jitter tolerance
eye diagram
equalizer
Issue Date: 16-Sep-2011
Abstract: This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.
URI: http://hdl.handle.net/1807/29987
Appears in Collections:Master

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