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Please use this identifier to cite or link to this item: http://hdl.handle.net/1807/32567

Title: Reusable OpenCL FPGA Infrastructure
Authors: Chin, Stephen Alexander
Advisor: Chow, Paul
Department: Electrical and Computer Engineering
Keywords: FPGA
OpenCL
SDRAM
Issue Date: 25-Jul-2012
Abstract: OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element - the memory interface. An Aggregating Memory Controller that aims to maximize bandwidth to external, large, high-latency, high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed, simulated, and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.
URI: http://hdl.handle.net/1807/32567
Appears in Collections:Master

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